(1) Field of the Invention
The present invention relates to a solid-state imaging device and an imaging system and, more particularly, to a Metal Oxide Semiconductor (MOS) solid-state imaging device which includes an analog-digital converter (ADC) for each of columns and can operate at high speed and an imaging system using such a solid-state imaging device.
(2) Description of the Related Art
There have recently been proposed many techniques for speeding up a MOS solid-state imaging device. Examples of the techniques include ones disclosed in Japanese Unexamined Patent Application Publication No. 2005-347932 (hereinafter referred to as Patent Document 1) and Japanese Unexamined Patent Application Publication No. 2001-045375 (hereinafter referred to as Patent Document 2).
The technique disclosed in Patent Document 1 will first be described.
Patent Document 1 discloses a MOS solid-state imaging device which includes a pixel unit composed of pixel circuits arranged in a matrix, each of which includes a photoelectric conversion element, and ADCs, each two or more of which are provided for each of columns of the matrix, and achieves higher-speed operation by sequentially reading out outputted signals as photoelectric conversion results from the pixel circuits in different rows of each column and processing, in parallel, the signals outputted by the corresponding two or more ADCs. Patent Document 1 also proposes a technique for achieving further speedup by providing a plurality of vertical signal lines for each of the columns and simultaneously reading out signals outputted from the pixel circuits in the different rows of each column.
With reference to FIGS. 1 to 6, the MOS solid-state imaging device disclosed in Patent Document 1 in which two ADCs are provided for each of the columns will be described below.
FIG. 1 is a block diagram showing a functional configuration of the solid-state imaging device. For illustrative simplicity, the description will be given using a pixel unit 11 which is composed of a plurality of pixel circuits 10 arranged in a matrix with three rows and six columns.
Outputs of the pixel circuits 10 in each column are commonly connected to a vertical signal line 12. A vertical scan circuit 13 sequentially outputs a read signal to the pixel circuits 10 in the rows. Upon receipt of a read signal, the pixel circuits 10 in each row output analog signals as photoelectric conversion results to the vertical signal lines 12.
Correlated double sampling circuits (hereinafter referred to as CDSs) 14 and 18 are each composed of individual circuits which are provided for the respective columns. The individual circuits in each column remove noise from the analog signals obtained from the pixel circuits in the different rows of the column. ADCs 151 and 191 are each composed of individual circuits which are provided for the respective columns. The individual circuits in each column convert the analog signals into digital signals after the noise removal in the CDSs 14 and 18.
The digital signals obtained after the conversion are sequentially outputted to the outside through data buses 17 and 21 one column at a time in accordance with selection signals from horizontal scan circuits 16 and 20. Since the data buses 17 and 21 transmit the digital signals obtained after the conversion, they can operate at high speed.
FIG. 2 shows a basic circuit configuration of an ADC 151 together with the data buses 17 and horizontal scan circuit 16. FIG. 2 shows circuits of the ADC 151 corresponding to three of the columns in a case where each of them is a single-slope integration analog-digital conversion circuit, and each digital signal is represented by three bits.
A portion of the ADC 151 corresponding to one column is made up of a comparator 22, a transfer switch 27 composed of three MOS transistors whose gates are connected to the output of the comparator 22, a memory 50 composed of three capacitances respectively connected to the three MOS transistors of the transfer switch 27, and a read switch 36 composed of three MOS transistors respectively connected to three capacitances of the memory 50. The ADC 151 includes the same circuits corresponding to the columns of the pixel unit.
A ramp generator 23 generates a single-slope ramp signal and supplies the signal to the comparators 22 through a signal line 24. A counter circuit 25 generates a counter code for counting a 3-bit value during a slope period of the ramp signal and supplies the counter code to the transfer switches 27 through signal lines 26.
The comparator 22 outputs a control signal to the transfer switch 27 when the level of the ramp signal and that of an analog signal supplied from the CDS 14 are equal. As a result, a value of the counter code is stored in the memory 50 through the transfer switch 27.
Gates of the three MOS transistors constituting the read switch 36 are connected to the horizontal scan circuit 16. The horizontal scan circuit 16 sequentially outputs a selection signal to the read switches 36 one column at a time, thereby sequentially outputting counter codes stored in the memories 50 in the columns to the outside through the data buses 17.
Note that the ADC 191, data buses 21, and horizontal scan circuit 20 are configured in the same manner as in the configuration shown in FIG. 2.
FIG. 3 is a diagram for conceptually explaining operation of a conventional solid-state imaging device. FIG. 3 schematically shows circuits corresponding to two of the columns of the solid-state imaging device in FIG. 1.
The vertical scan circuit 13 controls switches 38, such as MOS transistors, which are connected to the CDS 14 to be turned on when it supplies a read signal to the pixel circuits in one of the rows (e.g., A11 and A12). As a result, noise is removed from analog signals obtained from the pixel circuits in the row by the CDS 14, and the analog signals after the noise removal are converted into digital signals by the ADC 151.
The horizontal scan circuit 16 sequentially outputs a selection signal to the read switches 36 one column at a time to turn them on. With this operation, the digital signals obtained after the conversion in the ADC 151 are sequentially outputted to the outside through the data buses 17 one column at a time.
The vertical scan circuit 13 also controls switches 39 which are connected to the CDS 18 to be turned on when it supplies a read signal to the pixel circuits in another of the rows (e.g., A21 and A22). As a result, the noise is removed from the analog signals obtained from the pixel circuits in the row by the CDS 18, and the analog signals after the noise removal are converted into digital signals by the ADC 191.
In the above-described manner, the analog signals from the pixel circuits in different ones of the rows are distributed between upper and lower structures and are processed.
FIG. 4 is a timing chart for explaining operation timing. Two belts indicate times when series of operations for different ones of the rows, i.e., reading of analog signals from the pixel circuits in the different rows, noise removal by the CDSs, analog-digital conversion of the signals by the ADCs, and outputs of digital signals obtained after the conversion are performed. A direction from left to right in FIG. 4 corresponds to the passage of time.
Since each column has only one vertical signal line 12, a reading operation is sequentially performed for the rows one at a time. However, the other operations can be performed in parallel by the CDSs, ADCs, and data buses provided in two sets. This allows high-speed operation.
In order to achieve further speedup, two vertical signal lines 121 and 122 are provided for each of columns in a solid-state imaging device shown in FIG. 5. The vertical signal lines 121 connect the outputs of pixel circuits in odd-numbered rows to a CDS 14 while the vertical signal lines 122 connect the outputs of pixel circuits in even-numbered rows to a CDS 18. A vertical scan circuit 131 supplies a read signal simultaneously to the pixel circuits in one of the odd-numbered rows and those in one of the even-numbered rows.
With this configuration, all operations for two of the rows, including reading of the analog signals from the pixel circuits, can be simultaneously performed, as shown in FIG. 6. This allows higher-speed operation.
The technique disclosed in Patent Document 2 will be described next.
FIG. 7 is a circuit diagram showing a configuration of a solid-state imaging device disclosed in Patent Document 2.
The solid-state imaging device includes pixel circuits 1 and 2 arranged in a matrix, each of which includes a photoelectric conversion element, capacitance units 3 and 4 which accumulate, as analog charges, noise components before photoelectric conversion and optical signals as photoelectric conversion results from the pixel circuits 1 and 2, and switch circuits 5 and 6 which selectively output the noise components and optical signals stored in the capacitance units 3 and 4. The noise components are used for noise removal from a corresponding optical signal, and the noise removal can be achieved by subtracting the noise components from the corresponding optical signal.
According to the solid-state imaging device, for example, while noise components and optical signals from the pixel circuits 1 are accumulated in the capacitance units 3, noise components and optical signals from the pixel circuits in the other row which have been accumulated in the capacitance units 4 are outputted. After that, while noise components and optical signals from the pixel circuits 2 are accumulated in the capacitance units 4, the noise components and optical signals from the pixel circuits 1 accumulated in the capacitance units 3 are outputted. That is, it is possible to perform a process of alternately and in parallel accumulating and outputting the noise components and the optical signals from the pixel circuits in the different rows (referred to as background processing).
For this reason, the solid-state imaging device can cover up a horizontal blanking period for reading out noise components and optical signals from the pixel circuits in a row to the corresponding capacitance units with a period for outputting noise components and optical signals read out in advance from the pixel circuits in another row to the other capacitance units. As a result, it is possible to continuously output signals from the pixel circuits in the plurality of rows at high speed.
As described above, conventional solid-state imaging devices are effective to a certain degree in speeding up operation. Although the demand for higher-speed operation of solid-state imaging devices is expected to grow in the future along with a further increase in the number of pixels, it is difficult to meet the demand only by conventional techniques.
As measures for speedup, for example, an increase in an operating speed of the ADCs is conceivable for the solid-state imaging devices disclosed in Patent Document 1, and an increase in horizontal transfer rate is conceivable for the solid-state imaging device disclosed in Patent Document 2.
However, since circuits which are expected to be packed more densely in the future with an increase in the number of pixels need to be operated at higher speed while maintaining precision and stability, it is not always easy to take such measures. In particular, it is technically extremely difficult to take the measures in an analog circuit.